Building manycore processor-to-DRAM networks using monolithic silicon photonics

Modern embedded systems already include dozens of cores on a single die and this number is expected to increase over the next decade. Corresponding increases in main memory bandwidth, however, are also required if the greater core count is to result in improved application performance. Projected future enhancements of existing electrical DRAM interfaces, such as XDR and FB-DIMM, are not expected to meet bandwidth demands with reasonable power consumption and packaging cost. We propose to solve this manycore-to-memory bandwidth problem by combining monolithic silicon photonic technology that supports dense wavelength-division multiplexing (DWDM) and a hybrid opto-electrical processor-memory network architecture.